| Joe Gajda is recognized worldwide for his leadership in
metallographic techniques and physical failure analysis of semiconductor devices.
His 35 years of experience in semiconductor failure analysis includes organizing failure
analysis laboratories for Sprague Electric and IBM. He holds many patents on
metallographic techniques designed to obtain maximum information from an IC sample.
Joe has published over 20 papers. Joe was co-author of the paper "Semiconductor
Structure Enhancement for SEM Analysis", presented at the 1981 ISTFA (International Symposium for Testing and Failure
Analysis) which was recognized as an outstanding paper. He has presented invited
tutorials for both ISTFA and IRPS (International Reliability
Physics Symposium). Joe is available through his own company, J2 FA Diagnostics, for consulting and hands on instruction. Joe can be reached at J2FADiag@AOL.com or by phone at (512) 218-4941. |
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