In today's global style of semiconductor manufacturer, reliability problems may be found (or created) by the end user, by the design house, or by fabrication, assembly, and test organizations in-between.  This practical seminar is designed for failure analysts and other personnel working to solve reliability problems from any point in the semiconductor sequence.

Successful resolution of reliability problems requires participation of several companies in the manufacturing chain.  The failure analysis process is made more difficult by the fact that no one company has complete knowledge or control.

This Failure Analysis for Yield Enhancement Seminar defines a proven  approach applicable at any point in the semiconductor life cycle.  Essential problem solving concepts apply to the company with primary responsibility for analysis and to those involved on a support basis.  This seminar is designed to increase the effectiveness of failure analysis efforts at every point.

During the analysis of a problem, communication among the involved companies is an important key to rapid success.  This course includes examples of questions to ask and answers to look for to keep the analysis focused.  Ideas are presented to evaluate proposed corrective actions in light of conclusions made.

The 38-hour course (5 days) provides engineers and technicians a comprehensive overview of manufacturing defect mechanisms and the failure analysis techniques to identify them.  Emphasis is placed on simple methods not always requiring very expensive in-house analytical tools.  However, the capabilities of sophisticated analytic and fault location tools, as well as how best to utilize contract services are discussed in detail.

Statistical and defect density tools have produced great progress in manufacturing yields.  When those tools fail to identify the cause of yield loss, failure analysis techniques are the fastest and most economical way to determine and correct the cause.

The Instructor/Authors are failure analysts with experience in the solution of problems associated with semiconductor yield loss and reliability.  They welcome and encourage participants’ problems and questions:

  David L Burgess, owner, Accelerated Analysis

  Richard A Blanchard, PhD, Consultant

The book, Wafer Failure Analysis for Yield Enhancement, now available for purchase, is a comprehensive text written from the analysts' perspective.  Each participant will receive a copy as a lasting reference as well as a focus for lectures and work sessions during the seminar.